1. Technical Field of the Invention
This invention relates generally to electronic amplifiers, and more specifically to a differential (bridged) amplifier which has multiple power rails and uses an improved method of selecting rails to improve power efficiency.
2. Background Art
Class A and AB amplifiers are highly inefficient. Class D amplifiers are somewhat more efficient, but have a tradeoff of reduced linearity and increased cost. Class D amplifiers also suffer from high quiescent dissipation, which is the power dissipation when no input signal is present. Class D amplifiers also typically require an output low-pass filter, increasing component count and cost. Class A, AB, and D amplifiers use a single pair of power rails, typically referred to as VCC and VSS, or VCC and GND.
The ST Microelectronics TDA7563 is a car audio amplifier chip which uses two Class AB amplifiers to drive the ends of a bridged load. At any given time, only one of the two amplifiers is on, and the other is off. The on amplifier drives the full signal at one end of the load, and the off amplifier is simply switched to GND. As the output signal changes polarity, the two amplifiers alternate states. This cuts the power dissipation roughly in half, versus a conventional Class AB configuration.
Class G amplifiers are becoming a very good alternative to Class A, AB, and D amplifiers in some applications. Class G amplifiers use more than a single pair of power rails to improve efficiency. They rapidly switch between power rails, using the lowest power rail (for the output devices) that will accommodate the input signal at any given moment. Some use digital lookahead techniques to improve their switching performance. The theoretical maximum efficiency of a Class G amplifier increases as the number of power rails is increased, theoretically approaching 100% as the number of power rails approaches infinity. Unfortunately, increasing the number of power rails requires adding more power supply circuits and supply transition circuits, which increases system cost, complexity, and size. As a result, Class G amplifiers have been adopted in only a few markets.
In some applications, a load is driven by two bridged Class G amplifiers. In this configuration, both terminals of the load are driven in differential fashion. The load common mode is centered around a quiescent point which is normally the highest supply voltage (VCC) divided by two.
The principal goal in improving efficiency is to minimize the potential drop between any amplifier output terminal at any given instant in time and the power supply rail that is providing current to that output terminal. This reduces the P=VI dissipation experienced by the amplifier's output stage(s).
FIG. 1 illustrates an example of two bridged class G amplifiers (A0 and A1) driving a load. In this example, VCC4-0>VCC3-0>VCC1-0>VCC0-0 and VCC4-1>VCC3-1>VCC1-1>VCC0-1. In this example, the load is resistive and a signal is present that causes the load to be biased between supply voltage VCC3-0 and VCC1-1. The four power rails may be, for example: VCC0=0v, VCC1=1v, VCC3=3v, and VCC4=4v, but any other ascending set of values could be used instead. The term VCC2 is not used in this example, to avoid confusion with the 2v common mode point for the amplifiers. The -0 or -1 suffix on the power rails denotes whether the power rail is for the first amplifier A0 or the second amplifier A1.
In the example case of FIG. 1, the voltage across the load is less than VCC3-0 minus VCC1-1. The current that flows through the load in this example flows between supplies VCC3-0 and VCC1-1.
FIG. 2 illustrates another amplifier system according to the prior art. The amplifier system includes a first complementary pair NPN0, PNP0 and a second complementary pair NPN1, PNP1, each coupled to drive a load.
The collector of the NPNO transistor is coupled to the VCC4-0 rail through a first switch SW1 and to the VCC3-0 rail through a first diode D1. The collector of the PNP0 transistor is coupled to the VCC0-0 rail through a second switch SW2 and to the VCC1-0 rail through a second diode D2. The collector of the NPN1 transistor is coupled to the VCC4-1 rail through a third switch SW3 and to the VCC3-1 rail through a third diode D3. The collector of the PNP1 transistor is coupled to the VCC1-0 rail through a fourth switch SW4 and to the VCC1-0 rail through a fourth diode D4.
First driver logic (Driver 0) receives an input signal, and provides gate signals to the first complementary pair based on the input signal. A second driver (Driver 1) receives an input signal, and provides gate signals to the second complementary pair based on the input signal. If the input signals are large enough that the outer rails must be used, the drivers activate their switches to couple the outer rails to the complementary pairs. The diodes prevent the inner rails from being shorted to the outer rails when the switches are activated. When the input signals are small enough that only the inner rails are needed, the drivers deactivate the switches, and the complementary pairs are powered by the inner rails (less a junction drop through the diodes).
FIG. 3 illustrates another amplifier system according to the prior art, such as may be used in implementing portions of FIG. 2. The amplifier system includes amplifier output devices, a driver, and a rail selector, each denoted by a dashed box.
The output devices include a complementary pair whose emitters drive the output node of the amplifier. The complementary pair's collectors are coupled to the switched positive supply and switched negative supply, respectively.
The rail selector includes a first comparator (Comp 1) which compares the signal at the output node to the VCC3-0 inner rail less a Delta V1 drop and generates the signal which closes the first switch (SW1 in FIG. 2). The rail selector includes a second comparator (Comp 2) which compares the signal at the output node to the VCC1-0 inner rail plus a Delta V2 drop and generates the signal which closes the second switch (SW2 in FIG. 2). Delta V1 and Delta V2 provide for adequate margin between the value of the output voltage and the VCC3 and VCC1 rails, respectively, to ensure the output voltage does not collide with the rails.
FIGS. 4A-C illustrate a more comprehensive set of the various current paths that may be used when two bridged Class G amplifiers (amplifier 0 and amplifier 1) are used to drive a load, as in FIG. 1. The current path shown in FIG. 1 in this case would be the same as the line from VCC3-0 to VCC1-1 in FIG. 1. A four-rail Class G amplifier can be thought of as though it were switching between two Class AB amplifiers—one tied from VCC3 to VCC1, and the other tied from VCC4 to VCC0, in the example shown.
There are four possible current paths in this example: VCC4-0 to VCC0-1, VCC3-0 to VCC1-1, VCC4-1 to VCC0-0, and VCC3-1 to VCC1-0. The combinations from VCC3 to VCC1 dissipate less power than the combinations from VCC4 to VCC0, but they can only accommodate signal swings of more limited amplitude. The bridged Class G amplifier will use the VCC3 to VCC1 combinations when the input signal is not swinging far from the VCC2 common mode point (specifically, the voltage across the load is less than VCC3 minus VCC1). When the input signal swings too far from VCC2 for the VCC3 to VCC1 combinations to provide adequate voltage, the amplifier will transition to using the VCC4 to VCC0 combinations.
The lowest power supply rail may be GND, if desired. Alternatively, the lower half of the rails may be negative, with the common mode point set at GND. Other settings can also be used, as is known.
During periods of small signal operation, the amplifier is able to use its inner rails, shown in FIG. 4A as “State 1”. The positive side amplifier (Amplifier 0) uses rails VCC3-0 and VCC1-0, while the negative side amplifier (Amplifier 1) uses rails VCC3-1 and VCC1-1. The dashed boxes indicate the rails that are used. The solid lines through the load indicate the flow of current through the load. When a positive input signal is present, current flows from rail VCC3-0 through the load to rail VCC1-1, and when a negative input signal is present, current flows from rail VCC3-1 through the load to rail VCC1-0.
During periods of large signal operation, the amplifier cannot use its inner rails, and must shift to its outer rails, shown in FIG. 4B as “State 2” and “State 3”. The positive side amplifier (Amplifier 0) uses rails VCC4-0 and VCC0-0, while the negative side amplifier (Amplifier 1) uses rails VCC4-1 and VCC0-1. When a positive input signal is present, current flows from rail VCC4-0 through the load to rail VCC0-1, and when a negative input signal is present, current flows from rail VCC4-1 through the load to rail VCC0-0.
FIG. 11 is a signal waveform graph illustrating the behavior of the positive side upper switched rail, the negative side upper switched rail, the positive side lower switched rail, and the negative side lower switched rail, as determined in response to the actual positive output and negative output signals by a prior art system such as that of FIGS. 2 and/or 3. In this example, the output signals constitute triangle or “sawtooth” waves. The rail suffixes -0 and -1 are omitted, in the interest of clarity; the reader should understand that when a positive switched rail is said to be at e.g. VCC3, that implies VCC3-0, and that when a negative switched rail is said to be at e.g. VCC3, that implies VCC3-1. The reader should ignore the tiny vertical offsets between the signals, e.g. between times t3 and t4; those are for illustration only, to make all the lines visible by avoiding overlap, and are not intended to represent any actual behavior of the circuitry.
At time t0, the positive and negative outputs are at the “zero crossing” point (often VCC/2 in many systems, or VCC4/2 in this example), and the positive side upper switched rail is at VCC3 and the negative side lower switched rail is at VCC1 (the inner rails). At time t1, the positive output has approached VCC3, so the positive side upper switched rail is switched to VCC4, and the negative output has approached VCC1, so the negative side lower switched rail is switched to VCC0. The positive side lower switched rail remains at VCC1, and the negative side upper switched rail remains at VCC3. At time t2, the triangle wave peaks. At time t3, the positive output has fallen sufficiently below VCC3, and the positive side upper switched rail is switched back to VCC3, and the negative output has risen sufficiently above VCC1, and the negative side lower switched rail is switched back to VCC1.
At time t4, the positive output has fallen sufficiently close to VCC1, and the positive side lower switched rail is switched to VCC0, and the negative output has risen sufficiently close to VCC3, and the negative side upper switched rail is switched to VCC4. At time t5, the triangle wave peaks. At time t6, the positive output has risen sufficiently above VCC1, and the positive side lower switched rail is switched back to VCC1, and the negative output has fallen sufficiently below VCC3, and the negative side upper switched rail is switched back to VCC3.
The cycle then continues as illustrated.
FIG. 11 also identifies periods when the amplifiers are operating in State 1, State 2, or State 3. It should be noted that multiple rails (in this case two at a time) switch simultaneously when entering or exiting either State 2 or State 3. When rail switching events are ganged in a manner such as this, the number of total rail combinations is relatively few, which limits one's options in the quest to maximize power efficiency.
The prior art system is only able to operate at the inner rails VCC3 and VCC1 between times t3 and t4, and t6 and t7. This does not offer significant power savings versus simply operating at VCC4 and VCC0 all the time, in the particular example shown, using a sawtooth wave and evenly spaced power rails.
What is needed is an improved Class G Type amplifier which uses an improved rail selection method to improve efficiency.